In very large scale integration (VLSI) design, Boolean logic expressions are realized through networks of combinational logic gates. The combinational logic gates come in many varieties including pass logic transistor networks and restoring logic transistor networks. The pass and restoring transistor networks of the combinational logic gates are typically realized as metal on semiconductor field effect transistors (MOSFET).
A schematic of a MOSFET is depicted in FIG. 1. The MOSFET has a source 10, a drain 12 and a gate 14. The gate 14 is coupled to a control signal that dictates whether the input signal passes from the source 10 through the gate 14 to the drain 12 as output. In particular, if the control signal places the gate 14 in a high-impedance state, the input signal does not pass through the gate 14. On the other hand, if the control signal places the gate 14 in a conductive state, the input signal from the source 10 is conducted and passes as an output signal to the drain 12. When employed in this manner, the MOSFET acts as a simple switch.
The MOSFET may be either an N or P type MOSFET. In an N type MOSFET, the substrate is comprised of a P-semiconductor material. When the N type MOSFET conducts, the current carries electrons. With a P type MOSFET, in contrast, the substrate is comprised of N-semiconductor material, and as a result, the current carries holes rather than electrons. A plurality of N MOSFETs coupled together, constitute an N network. Similarly, a plurality of P MOSFETs coupled together form P networks.
Pass logic networks and restoring logic networks may be comprised of both P networks and N networks. The distinction between pass logic networks and restoring logic networks lies in how the networks employ the inputs of the networks combinational logic function. Restoring logic networks employ the inputs to control the gates 14 of the MOSFET's. The source 10 of the MOSFET is tied either high or low, and it is one of these fixed values which is passed from the source 10 to the drain 12 of a MOSFET. This fixed value is passed when the signal applied to the gate 14 puts the transistor in a conducting state. Pass logic networks, however, employ the inputs differently. They employ the inputs as both signals that control the gate 14, and values that are passed from the source 10 to the drain 12.
Example restoring logic networks are shown in FIGS. 2a and 2b. In particular, FIG. 2a shows an N restoring logic network that is tied to a ground (low). The combinational inputs for this network are X.sub.1, . . . ,X.sub.n. FIG. 2b shows a similar restoring logic network, but this network is a P restoring network which is tied to a voltage source (high). The combinational inputs X.sub.1, . . . ,X.sub.n are applied as control signals in this network.
FIGS. 2c and 2d depict pass logic networks for a given combinational input Z. In FIG. 2c, an N pass network is shown. FIG. 2d shows a P pass network. Note that all of the control signals are complemented in the P pass network. In both of these pass networks the combinational input Z may assume a value of either 1 or 0.
VLSI designers often desire to use both pass logic networks and restoring logic networks in designing integrated circuits. Currently, however, automated generation of combinational logic has focused exclusively on integrated circuits having only restoring logic networks. As such, if a designer desires to use pass logic networks in his integrated circuit design, he cannot utilize an automated generation approach. This is especially problematic given the significant advantages of including pass logic networks in integrated circuit designs. For instance, pass logic networks (often) generate smaller (and/or faster) integrated circuits. Smaller integrated circuits are cheaper to produce while faster integrated circuits yield higher performance products.